Thermal management of electrical components, e.g., packaged integrated circuits (ICs), is becoming a greater concern due to the ever shrinking sizes of the components themselves and the systems, e.g., portable electronic devices such as smartphones and tablet computers, they are integrated into. The extraction of heat from small, tightly spaced components is simultaneously becoming more difficult and more important to ensure electrical components operate as intended. Additionally, components are beginning to be manufactured to include multiple co-packaged die, which may come with thermal management concerns of their own. The numerous interfaces these co-packaged die include may increase the barrier to thermal dissipation regardless of the packaging. The internal increases in temperature due to reduced thermal conduction of components and co-packaged die may exceed their operation specifications, which may prevent components from functioning properly. As a result, improvements in heat extraction from semiconductor components may be desired.
Until relatively recently, most packaged semiconductor components included one or two separate die in a single package. With only one or two co-packaged die, heat extraction and dissipation was relatively straight forward. In these scenarios, heat extraction improvements may have simply been obtained by utilizing larger heat sinks, for example. However, as the number of co-packaged die increases, the potential for thermal problems also increases. The increase in thermal problems, e.g., poor heat dissipation/extraction from a stack of die, may partially be due to the distance the heat may need to travel to reach a heat sink or the package and potentially compounded by the number of interfaces which the heat may travel through. Once the heat reaches the heat sink and/or the package, the heat may be dissipated into the surrounding environment. The heat may be generated in active regions of co-packaged die which may be separated from the heat sink by other die. For example, one or more of the co-packaged die may have an active region on a surface of the die, where the active regions include transistors and connections configured to perform operations. The surface that includes the active regions may be separated by the die and/or other die from a heat sink, for example.
The interfaces may be a result of the semiconductor design and resulting fabrication process. For example, a stack of semiconductor die may be electrically interconnected and co-packaged so they operate as a single component capable of performing various functions. Some of the die in the stack, die in the middle of the stack for example, may experience heat increases above normal operating temperatures. This heat, however, may have a less direct path to a heat sink, which may cause the heat to dissipate slower than desired. The indirect path may be partially due to the number of interfaces, e.g., metal, passivation layers, other die in the stack, and so on, which may limit the extraction of the heat. A potential result may be the die in the middle, as in the example, experiencing active region temperatures above specified operating temperatures, which may result in poor performance or inoperability.